WM8903
REVISION HISTORY
DATE
21/07/11
REV
4.1
ORIGINATOR
SS
08/08/11
4.2
PH
28/09/11
4.3
01/03/12
4.4
PH
JMacD
01/03/12
4.4
01/03/12
4.4
14/06/12
4.5
JMacD
JMacD
SS
Production Data
CHANGES
Correction to Audio Interface, Slave Mode specifications. “DACDAT set-up
time to BCLK rising edge” specification changed to 20ns minimum.
All Read-Only and Write-Only registers are specifically identified as Read-
Only or Write-Only respectively.
LIN_VOL and RIN_VOL registers updated; 00000 = -1.55dB
Order codes updated from WM8903LGEFK/V and WM8903LGEFK/RV to
WM8903CLGEFK and WM8903CLGEFK/R to reflect change to copper wire
bonding
MSL level changed from MSL3 to MSL1
Package Diagram changed to DM110.A
Correction to Audio Interface, Slave Mode specifications. “ADCDAT
propagation delay from BCLK falling edge” specification changed to 30ns
maximum.
w
PD, Rev 4.5, June 2012
178