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X28C512DMB-15 查看數據表(PDF) - Intersil
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产品描述 (功能)
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X28C512DMB-15
5V, Byte Alterable EEPROM
Intersil
X28C512DMB-15 Datasheet PDF : 25 Pages
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DATA Polling Timing Diagram (Note 7)
X28C512, X28C513
Address
A
n
A
n
A
n
CE
WE
t
OEH
OE
I/O
7
D
IN
= X
Toggle Bit Timing Diagram
CE
D
OUT
= X
t
WC
t
OES
t
DW
D
OUT
= X
WE
t
OEH
OE
HIGH Z
I/O
6
*
*
t
WC
*Starting and ending state will vary, depending upon actual t
WC
.
NOTE:
7. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
t
OES
t
DW
17
FN8106.1
September 29, 2005
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