PT2396-S 查看數據表（PDF） - Princeton Technology

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PT2396-S

Digital Echo/Surround Processor IC

Princeton Technology 

Tel: 886-2-66296288

Fax: 886-2-29174598

URL: http://www.princeton.com.tw

Digital Echo/Surround Processor IC

PT2396

Notes:

1. Dimensioning and tolerancing per ANSI Y 14.5-1982.

2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold Flash,

protrusion or gate burrs shall not exceed 0.15mm (0.006 in)per side.

3. Dimension “E” does not include interlead flash protrusions. Interlead flash or protrusions shall not

exceed 0.25 mm (0.010 in) per side.

4. The chamfer on the body is optional. It is not present, a visual index feature must be located within

the crosshatched area.

5. “L” is the length of the terminal for soldering to a substrate.

6. “N” is the number of terminal position. (N=24)

7. The lead width “B” as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not

exceed a maximum value of 0.61mm (0.24 in).

8. Controlling dimension: MILLIMETER.

9. Refer to JEDEC MS-013, Variation AD.

JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.

PT2396 V1.4

- 18 -

December, 2005

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