XE1203 查看數據表（PDF） - Unspecified

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XE1203

433MHz / 868MHz / 915MHz Low-power, integrated UHF transceiver

Unspecified 

Data Sheet

XE1203

5 INTERFACE DEFINITION, PRINCIPLES OF OPERATION

5.1 SERIAL CONTROL INTERFACE

A 3-wire bi-directional bus (SCK, SI, SO) is used to communicate with XE1203. SCK and SI are input signals

supplied externally, for example by the microcontroller. The XE1203 configures the SO signal as an output pin

during read operation, and it is tri-stated in other modes. The falling edge of the SCK signal is used to sample the

SI pin to write data into the internal shift register of the XE1203. The rising edge of the SCK signal is used to output

data to SO pin by XE1203, so the microcontroller should sample data at the falling edge of SCK.

The signal EN must be low during the whole write and read sequences. In write mode the actual content of the

configuration register is updated at the rising edge of the EN signal. Before this, the new data is stored in

temporary registers whose content does not affect the transceiver settings.

The timing diagram of a write sequence is given in the figure below. The sequence is initiated when a Start

condition is detected, that is when the SI signal is set to “0” during a period of SCK. The next bit is a read/write

(R/W) bit which should be “0” to indicate a write operation. The next 5 bits are the address of the control register

A[4:0] to be accessed, MSB first. Then, the next 8 bits are the data to be written in the register. The sequence ends

with 2 stop bits set to “1”. The data on SI should change at the rising edges of SCK, and is sampled at the falling

edge of SCK. After the 2 stop bits, the data transfer is terminated. The SI line should be at “1” for at least one clock

cycle on SCK before a new write or read sequence can start. In doing this, users can do multiple registers write

without rising EN signal in between. The duty cycle of SCK must be between 40 % and 60 % and the maximum

frequency of this signal is 1 MHz except when reading the RSSI output and FEI output where the maximum

frequency of SCK is limited to 100 KHz. Over the operating supply and temperature range, set-up and hold time for

SI on the falling edge of SCK are 200ns.

The register at address 0 is one bit length and used to define the configuration of the chip. When writing in this

register, the sequence described above is valid except that only one bit data is needed instead of 8 bits. If a unique

write procedure is used for all registers then, when writing at address 0, 8 data bit are sent but only the MSB is

valid and written at address 0. The remaining 7 data bits must be all ones.

SCK

SI

EN

SO

A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

HZ

Figure 11 Write sequence into configuration register

The following figure shows a write sequence at address zero.

SCK

SI

EN

SO

A4

A3

A2

A1

A0 D7

HZ

Figure 12 Write sequence into configuration register at address zero.

19

D0308-214

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