Z801806FSC 查看數據表（PDF） - Zilog

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Z801806FSC

Microprocessor Unit

Zilog 

Z80180

Microprocessor Unit

14

RESET

Timer Data

Register

Timer Data Register

WRITE (0004h)

0 < t < 20 f

20 f 20 f 20 f 20 f 20 f 20 f 20 f 20 f 20 f

FFFFh 0004h

0003h 0002h 0001h 0000h 0003h 0002h 0001h 0000h 0003h

Timer Reload

Register

TDE Flag

Timer Reload Register WRITE (0003h)

FFFFh 0003h

WRITE a 1 to TDE

Reload

Reload

TIF Flag

Timer Data Register READ

Timer Control Requestor READ

Figure 5. Timer Initialization, Count Down, and Reload Timing

Timer Data

Timer Data

Reg. = 0001h Reg. = 0000h

f

TOUT

Figure 6. Timer Data Register

Clocked Serial I/O (CSIO). The CSIO channel provides a half-duplex serial transmitter and

receiver. This channel can be used for simple high-speed data connection to another micro-

processor or microcomputer. TRDR is used for both CSIO transmission and reception. The

system design must ensure that the constraints of half-duplex operation are met. Transmit

and Receive operations cannot occur simultaneously. For example, if a CSIO transmission is

attempted while the CSIO is receiving data, a CSIO does not work.

Note: TRDR is not buffered. Attempting to perform a CSIO transmit while the previous

transmit data is still being shifted out causes the shift data to be immediately

PS014004-1106

Architecture

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