Z893232YFEC 查看數據表（PDF） - Zilog
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Z893232YFEC Datasheet PDF : 61 Pages
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REGISTERS (Continued)
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
The Status Register
The status register can always be read in its entirety. S15-
S10 are set/reset by hardware and can only be read by
software. S9-S0 control hardware looping and can be
written by software (Table 8).
Table 8. RPL Description
S2
S1
S0
Loop Size
0
0
0
256
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
S15-S12 are set/reset by the ALU after an operation. S11-
S10 are set/reset by the user inputs. S6-S0 are control bits
described in Table 5. S7 enables interrupts. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiple/shift
option is used, then the shifter shifts the result three bits
right. This feature allows the data to be scaled and prevents
overflows.
PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.
Negative
Overflow
Zero
Carry
User Input 0-1
(Read Only)
MPY output arithmetically
shifted right by three bits
Overflow protection
N OV Z C UI1 UI0 SH3 OP IE UO1 UO0
RPL
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
* The output value is the opposite of the status register content.
Ram
Pointer
000
001
010
011
100
101
110
111
Loop
Size
256
2
4
8
16
32
64
128
"Short Form Direct" bits
User Output 0-1*
Global Interrupt Enable
Figure 7. Status Register
14
DS95DSP0101 Q4/95
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