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EP4CE10F17C6N

Cyclone IV FPGA Device Family

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Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

1–11

Figure 1–1 shows the structure of the Cyclone IV GX transceiver.

Figure 1–1. Transceiver Channel for the Cyclone IV GX Device

FPGA

Fabric

Transmitter Channel PCS

TX Phase

Compensation

FIFO

Byte Serializer

8B10B Encoder

Transceiver Channel

PMA

Receiver Channel PCS

Receiver Channel

PMA

f For more information, refer to the Cyclone IV Transceivers Architecture chapter.

Hard IP for PCI Express (Cyclone IV GX Devices Only)

Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)

in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that

implements the PHY-MAC layer, Data Link Layer, and Transaction Layer

functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point

configurations. This pre-verified hard IP block reduces risk, design time, timing

closure, and verification. You can configure the block with the Quartus II software’s

PCI Express Compiler, which guides you through the process step by step.

f For more information, refer to the PCI Express Compiler User Guide.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 1

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