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MX29LV320E 查看數據表(PDF) - Macronix International

零件编号
产品描述 (功能)
生产厂家
MX29LV320E
MCNIX
Macronix International MCNIX
MX29LV320E Datasheet PDF : 68 Pages
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MX29LV320E T/B
COMMON FLASH MEMORY INTERFACE (CFI) MODE
QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE
MX29LV320E T/B features CFI mode. Host system can retrieve the operating characteristics, structure and
vendor-specified information such as identifying information, memory size, byte/word configuration, operating
voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the
system writes the CFI Query command, 98H, to address 55h/AAh (depending on Word/Byte mode) any time the
device is ready to read array data. The system can read CFI information at the addresses given in Table 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the
CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select
mode. The CFI unused area is Macronix's reserved.
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Table 4-2. CFI Mode: System Interface Data Values
Description
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n us
Typical timeout for maximum-size buffer write, 2n us
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical
P/N:PM1575
30
Address (h) Address (h)
(Word Mode) (Byte Mode)
10
20
11
22
12
24
13
26
14
28
15
2A
16
2C
17
2E
18
30
19
32
1A
34
Data (h)
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Address (h) Address (h)
(Word Mode) (Byte Mode)
1B
36
1C
38
1D
3A
1E
3C
1F
3E
20
40
21
42
22
44
23
46
24
48
25
4A
26
4C
Data (h)
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
REV. 1.3, DEC. 19, 2013

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