FAN3223(2008) 查看數據表（PDF） - Fairchild Semiconductor

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FAN3223
(Rev.:2008)

Dual 4A High-Speed, Low-Side Gate Drivers

Fairchild Semiconductor 

Truth Table of Logic Operation

The FAN3225 truth table indicates the operational states

using the dual-input configuration. In a non-inverting

driver configuration, the IN- pin should be a logic LOW

signal. If the IN- pin is connected to logic HIGH, a disable

function is realized, and the driver output remains LOW

regardless of the state of the IN+ pin.

IN+

IN-

OUT

0

0

0

0

1

0

1

0

1

1

1

0

Operational Waveforms

At power-up, the driver output remains LOW until the

VDD voltage reaches the turn-on threshold. The

magnitude of the OUT pulses rises with VDD until

steady-state VDD is reached. The non-inverting

operation illustrated in Figure 50 shows that the output

remains LOW until the UVLO threshold is reached, then

the output is in-phase with the input.

In the non-inverting driver configuration in Figure 48,

the IN- pin is tied to ground and the input signal (PWM)

is applied to IN+ pin. The IN- pin can be connected to

logic HIGH to disable the driver and the output remains

LOW, regardless of the state of the IN+ pin.

VDD

PWM

IN+

IN- FAN3225

OUT

GND

Figure 48. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application in Figure 49, the IN+

pin is tied HIGH. Pulling the IN+ pin to GND forces the

output LOW, regardless of the state of the IN- pin.

VDD

Figure 50. Non-Inverting Start-Up Waveforms

For the inverting configuration of Figure 49, start-up

waveforms are shown in Figure 51. With IN+ tied to

VDD and the input signal applied to IN–, the OUT

pulses are inverted with respect to the input. At power-

up, the inverted output remains LOW until the VDD

voltage reaches the turn-on threshold, then it follows

the input with inverted phase.

VDD

Turn-on threshold

PWM

IN+

IN- FAN3225

OUT

GND

Figure 49. Dual-Input Driver Enabled,

Inverting Configuration

© 2007 Fairchild Semiconductor Corporation

FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5

IN-

IN+

(VDD)

OUT

Figure 51. Inverting Start-Up Waveforms

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