MCP6N16T-001 查看數據表（PDF） - Microchip Technology
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MCP6N16T-001 Datasheet PDF : 58 Pages
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MCP6N16
VIP
VIM
GA1
Low-Pass
Filter
VREF
GA2
VFG
FIGURE 4-6:
Second Chopping Clock
Phase; Simplified Diagram.
4.2.3
INTERMODULATION DISTORTION
(IMD)
These INAs will show intermodulation distortion (IMD)
products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
See Figures 2-75 and 2-76.
DS20005318A-page 40
4.3 Other Functional Blocks
4.3.1 RAIL-TO-RAIL INPUTS
Each input stage uses one PMOS differential pair at the
input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
crossover distortion vs. common mode voltage.
With this topology, the inputs (VIP and VIM) operate
normally down to VSS – 0.15V and up to VDD + 0.15V
at room temperature (see Figure 2-52). The input offset
voltage (VOS) is measured at VCM = VSS – 0.15V and
VDD + 0.15V (at +25°C) to ensure proper operation.
4.3.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-82 shows an input voltage
exceeding both supplies with no phase inversion.
The input devices also do not exhibit phase inversion
when the differential input voltage exceeds its limits;
see Figure 2-83.
4.3.1.2 Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-7. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
VDD
Bond
Pad
VIP
Bond
Pad
VSS
Bond
Pad
Input
Stage
of
INA Input
Bond
Pad
VIM
FIGURE 4-7:
Structures.
Simplified Analog Input ESD
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go too far above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events (that meet the specification) are limited so that
damage does not occur.
2014 Microchip Technology Inc.
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