74HCT74D-Q100 查看數據表（PDF） - NXP Semiconductors.
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74HCT74D-Q100 Datasheet PDF : 19 Pages
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Nexperia
74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1RD
1
1D
2
1CP
3
1SD
4
1Q
5
1Q
6
GND
7
2Q
8
2Q
9
2SD
10
2CP
11
2D
12
2RD
13
VCC
14
6. Functional description
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
complement output
ground (0 V)
complement output
output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
Table 3. Function table[1]
Input
nSD
nRD
nCP
nD
L
H
X
X
H
L
X
X
L
L
X
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Output
nQ
nQ
H
L
L
H
H
H
Table 4. Function table[1]
Input
nSD
nRD
nCP
nD
H
H
L
H
H
H
Output
nQn+1
L
H
nQn+1
H
L
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
74HC_HCT74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 December 2015
© Nexperia B.V. 2017. All rights reserved
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