AT88SC102 查看數據表（PDF） - Unspecified

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AT88SC102

1K EEPROM– Security Logic with Two Application Zones

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11. Micro Operations

The AT88SC102 circuit operation modes are selected by the input logic levels on the control pins

PGM, CLK, and RST and by the internal address. Timing for these operations is specified in the

AC Characteristics section.

Table 11-1. Micro Operations

Operation

PGM

RST

RESET

X

INC/READ

0

0

INC/CMP

0

0

CLK

0

Definition

This operation will reset the internal address to “0”. After the

falling edge of RST, the first bit of the fabrication zone

(Address 0) will be driven on the I/O contact. The erase

flags (E1 and E2) will be reset.

The address is incremented on the falling edge of CLK. If

read operations are enabled, the addressed bit will be

driven on the I/O pin after the falling edge of CLK. When

read operations are disabled, the I/O will be disabled and

pulled to a high state by the external system pull-up

resistor.

The INC/CMP operation will compare the value of the data

driven by the system host on the I/O pin to the value of the

bit already written into the EEPROM memory at that

address location. This process is used during validation of

the AT88SC102 security code and erase keys. The data

must be stable on the I/O pin before the rising edge of CLK

when the data will be latched internally. Comparison occurs

on the next falling edge of CLK. The internal address is also

incremented on the falling edge of CLK.

ERASE/WRITE

1

0

The I/O pin must be driven to a “1” for an erase and to a “0”

for a write operation before the rising edge of CLK (see tDS)

The device is placed in standby mode when FUS pin = “0”

STANDBY

0

1

X

and RST = “1”. The address will not increment when RST is

high.

Notes: 1. The output is disabled (hi-state) on all addresses where the read operation is disabled.

2. The two instructions INC/READ and INC/CMP share the same control signal states.

3. The circuit will distinguish between the INC/READ and INC/CMP instructions by testing the internal address counter.

(CMP can only be done with the addresses corresponding to the security code or to an erase key).

4. The internal address counter counts up to 1567. An additional CLK pulse resets the address to “0”.

12 AT88SC102

1419C–SMEM–6/08

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