AT88SC102 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

AT88SC102

1K EEPROM– Security Logic with Two Application Zones

Unspecified 

AT88SC102

12. Device Functional Operation

Table 12-1. Device Functional Operation

Name

Functional Operation Sequence

POR

OPERATION:

POR (power-on reset) is initiated as the device power supply ramps from 0V up to a valid operating voltage.

FUNCTION:

POR resets all flags, and the address is reset to “0”.

RESET

OPERATION:

With CLK low, a falling edge on the RST pin will reset the address counter to address “0”.

FUNCTION:

The address is reset to “0”, and the first bit of the memory is driven by the AT88SC102 on I/O after a reset. Only E1

and E2 are reset when the address is reset to 0. The Reset operation has no affect on any of the other flags (SV,

P1, R1, P2, R2).

ADDRESSING

OPERATION:

Addressing is handled by an internal address counter. The address is incremented on the falling edge of CLK.

Reset must be low while incrementing the address. A falling edge of reset clears the counter to address “0”.

FUNCTION:

Addressing of the AT88SC102 is sequential. Specific bit addresses may be reached by completing a reset, then

clocking the device (INC/READ) until the desired address is reached. The AT88SC102 will determine which

operations are allowed at specific address locations. These operations are specified in Tables 1 and 2.

For instance, to address the issuer zone (IZ), execute a reset operation, then clock the device 16 times. The device

now outputs the first bit of the IZ. After the address counter counts up to 1567, the next CLK pulse resets the

address to “0”.

READ

OPERATION:

RST and PGM pins must be low. If a read operation is allowed, the state of the memory bit being addressed is

output on the I/O pin. The I/O buffer is an open drain, and the output of a logic “0” therefore causes the device to pull

the pin to ground. The output of a logic “1” causes the device to place the pin in a high impedance state. So to

sense a logic “1”, an external pull-up must be placed between the I/O pin and VCC. The address counter is

incremented on the falling edge of CLK.

FUNCTION:

Non-application Zones:

As the address counter is incremented, the contents of the memory are read out on the I/O pin. The read operation

is inhibited for addresses where security prevents a read operation (see Tables 1 and 2).

Application Zones:

Application Zone 1 can be read when: SV = “1” or R1 = “1”.

Application Zone 2 can be read when: SV = “1” or R2 = “1”.

13

1419C–SMEM–6/08

Share Link: