AT88SC102 查看數據表（PDF） - Unspecified

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AT88SC102

1K EEPROM– Security Logic with Two Application Zones

Unspecified 

17. AC Load Circuit

Figure 17-1. AC Load Circuit

Test

Point

VCC

RLOAD

CHIP

I/O

100 pF

Test Ckt.

Included

AT88SC102

18. Timing Diagrams

18.1 Reset

Figure 18-1. Reset

Address

0 (internal address counter)

CLK

RST

I/O

tRH

tDVR

Output

Note: CLK should be low on the falling edges of RST. CLK may remain low while RST is pulsed.

Data Valid

19

1419C–SMEM–6/08

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