AT88SC102 查看數據表（PDF） - Unspecified

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AT88SC102

1K EEPROM– Security Logic with Two Application Zones

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18.4 Compare

Figure 18-4. Compare

Address

An-1

AT88SC102

An

An+1

CLK

tSC

tHC

tSC

I/O

Input

Note:

Input Data is latched on the rising edge of CLK. Comparison occurs on the next falling edge of CLK. The address counter is

incremented on the falling edge of CLK. During a compare operation of the first bit following a read (i.e., the first bit of the SC or

erase keys), data driven to the I/O may be delayed by tDV after the falling edge of CLK.

18.5 Security Code Validation

Figure 18-5. Security Code Validation

Reset

Read

Address Ax

A0

A1

A2

A79

Compare SC

(A)

A80

A81

A94

A95

Read SCAC

(B)

A96

A97

A98

A99

Write

(C)

Read Erase

(D)

(E)

Read

(F)

(G)

A100

RST

CLK

I/O

DX

D0

D1

Output

PGM

CD80

CD81

Input

CD95

0

0

0

Output

1

0

01

Input Input Output Input

D99

Output

SV flag

Notes: 1. An = Address, Dn = Read data (output), CDn = Compare data (input

2. Security Level 2 (issuer fuse blown).

A = Compare sequence of the security code.

B = This diagram shows an example in which the first three bits of the Security Code Attempts Counter (96–98) are previ-

ously set to “0”. Bit 99 in this example is a “1”, so the write/erase sequence is begun with that bit.

C = Write operation of a “0” over the existing “1”.

D = The AT88SC102 will output a “0” following the write operation. If the comparison is successful, the SV flag is set on the

falling edge of CLK and the SCAC zone can be erased.

E = Erase operation.

F = The AT88SC102 will output a “1” following the erase operation if the security code verification is successful. If invalid, the

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1419C–SMEM–6/08

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