AT91SAM9CN11-CFU 查看數據表（PDF） - Atmel Corporation

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AT91SAM9CN11-CFU

ARM-based Embedded MPU

Atmel Corporation 

 Programmable Wait State Generation

 External Wait Request

 Programmable Data Float Time

 Slow Clock mode supported

6.3.3

DDR-SDRAM Controller

 Supports DDR2-SDRAM, Low-power DDR1-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM

 Numerous Configurations Supported

 2K, 4K, 8K, 16K Row Address Memory Parts

 SDRAM with 4 Internal Banks

 SDR-SDRAM with 16-bit or 32-bit Data Path

 DDR-SDRAM with 16-bit Data Path

 One Chip Select for SDRAM Device (256 Mbytes Address Space)

 Programming Facilities

 Multibank Ping-pong Access (Up to 4 Banks or 8 Banks Opened at Same Time = Reduced Average Latency

of Transactions)

 Timing Parameters Specified by Software

 Automatic Refresh Operation, Refresh Rate is Programmable

 Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)

 Energy-saving Capabilities

 Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported

 SDRAM Power-up Initialization by Software

 CAS Latency of 2, 3 Supported

 Reset Function Supported (DDR2-SDRAM)

 ODT (On-die Termination) Not Supported

 Auto Precharge Command Not Used

 SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported

 DDR2-SDRAM with Eight Internal Banks Supported

 Linear and interleaved decoding supported

 Clock Frequency Change in Precharge Power-down Mode Not Supported

 OCD (Off-chip Driver) Mode Not Supported

6.3.4

Programmable Multi-bit Error Correcting Code (PMECC)

 Multibit Error Correcting Code.

 Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.

 Programmable Error Correcting Capability: 2, 4, 8, 16 and 24 bit of errors per block.

 Programmable block size: 512 bytes or 1024 bytes.

 Programmable number of block per page: 1, 2, 4 or 8 blocks of data per page.

 Programmable spare area size.

 Supports spare area ecc protection.

 Supports 8 kbytes page size using 1024 bytes/block and 4 kbytes page size using 512 bytes/block.

 Multibit Error detection is interrupt driven.

6.3.5

Programmable Multi-bit ECC Error Location (PMERRLOC)

 Provides hardware acceleration for determining roots of polynomials defined over a finite field

 Programmable finite Field GF(2^13) or GF(2^14)

 Finds roots of error-locator polynomial.

 Programmable number of roots.

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 26

11063K–ATARM–05-Nov-13

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