MG65PB02 查看數據表（PDF） - Oki Electric Industry

零件编号

产品描述 (功能)

生产厂家

MG65PB02

0.25µm Embedded DRAM/Customer Structured Arrays

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG63P/64P/65P s

Design Process

The following figure illustrates the overall IC design process, also indicating the three main interface

points between external design houses and Oki ASIC Application Engineering.

VHDL/HDL Description

Synthesis

Floorplanning

Gate-Level Simulation

Netlist Conversion

(EDIF 200)

Scan Insertion (Optional)

CDC [1]

Floorplanning

Pre-Layout Simulation

(Cadence Verilog)

Layout

Verification

(Cadence DRACULA)

Post-Layout Simulation

(Cadence Verilog)

Fault Simulation [6]

Manufacturing

Prototype

Test Program

Conversion

Test Vectors

LSF[2]

Level 1 [5]

CAE Front-End

Level 2

Test Vector Conversion

(Oki TPL [4])

TDC [3]

Level 2.5 [5]

Automatic Test

Pattern Generation

(Synopsys Test Compiler)

Oki Interface

Level 3 [5]

[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules

[2] Oki’s Link to Synthesis Floorplanning toolset (LSF) transfers post-floorplanning timing for resynthesis

[3] Oki’s Test Data Check program (TDC) verifies test vector rules

[4] Oki’s Test Pattern Language (TPL)

[5] Alternate Customer-Oki design interfaces available in addition to standard level 2

[6] Standard design process includes fault simulation

Figure 13. Oki’s Design Process

Oki Semiconductor

13

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