AD7482 查看數據表（PDF） - Analog Devices

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AD7482

3 MSPS, 12-Bit SAR ADC

Analog Devices 

AD7482

PARALLEL INTERFACE

The AD7482 features two parallel interfacing modes. These

modes are selected by the mode pins as detailed in Table III.

Table III. Operating Modes

Do Not Use

Parallel Mode 1

Parallel Mode 2

Do Not Use

Mode 2

0

0

1

1

Mode 1

0

1

0

1

In Parallel Mode 1, the data in the output register is updated on

the rising edge of BUSY at the end of a conversion and is avail-

able for reading almost immediately afterward. Using this mode,

throughput rates of up to 2.5 MSPS can be achieved. This

mode should be used if the conversion data is required immedi-

ately after the conversion has completed. An example where this

may be of use is if the AD7482 was operating at much lower

throughput rates in conjunction with the NAP Mode (for

power-saving reasons), and the input signal was being compared

with set limits within the DSP or other controller. If the limits

were exceeded, the ADC would then be brought immediately

into full power operation and commence sampling at full speed.

Figure 17 shows a timing diagram for the AD7482 operating in

Parallel Mode 1 with both CS and RD tied low.

In Parallel Mode 2, the data in the output register is not updated

until the next falling edge of CONVST. This mode could be used

where a single sample delay is not vital to the system operation

and conversion speeds of greater than 2.5 MSPS are desired.

This may occur, for example, in a system where a large amount

of samples are taken at high speed before a Fast Fourier Trans-

form is performed for frequency analysis of the input signal.

Figure 18 shows a timing diagram for the AD7482 operating in

Parallel Mode 2 with both CS and RD tied low.

Data must not be read from the AD7482 while a conversion is

taking place. For this reason, if operating the AD7482 at

throughput speeds greater than 2.5 MSPS, it will be necessary

to tie both CS and RD Pins on the AD7482 low and use a

buffer on the data lines. This situation may also arise in the case

where a read operation cannot be completed in the time after

the end of one conversion and the start of the quiet period before

the next conversion.

The maximum slew rate at the input of the ADC should be

limited to 500 V/␮s while BUSY is low to avoid corrupting the

ongoing conversion. In any multiplexed application where the

channel is switched during conversion, this should happen as

early as possible after the BUSY falling edge.

Reading Data from the AD7482

Data is read from the part via a 13-bit parallel databus with the

standard CS and RD signals. The CS and RD signals are inter-

nally gated to enable the conversion result onto the databus.

The data lines D0 to D12 leave their high impedance state when

both the CS and RD are logic low. Therefore, CS may be perma-

nently tied logic low if required, and the RD signal may be used to

access the conversion result. Figure 15 shows a timing specification

called tQUIET. This is the amount of time that should be left after

any databus activity before the next conversion is initiated.

Writing to the AD7482

The AD7482 features a user-accessible offset register. This allows

the bottom of the transfer function to be shifted by ± 200 mV.

This feature is explained in more detail in the Offset/Overrange

section.

To write to the offset register, a 13-bit word is written to the

AD7482 with the 10 LSBs containing the offset value in two’s

complement format. The 3 MSBs must be set to “0.” The offset

value must be within the range –327 to +327, corresponding to an

offset from –200 mV to +200 mV. The value written to the offset

register is stored and used until power is removed from the device,

or the device is reset. The value stored may be updated at any

time between conversions by another write to the device. Table IV

shows some examples of offset register values and their effective

offset voltage. Figure 16 shows a timing diagram for writing to

the AD7482.

Table IV. Offset Register Examples

Code (Dec)

–327

–128

+64

+327

D12–D10

000

000

000

000

D9–D0

(Two’s

Complement)

1010111001

1110000000

0001000000

0101000111

Offset

(mV)

–200

–78.12

+39.06

+200

Driving the CONVST Pin

To achieve the specified performance from the AD7482, the

CONVST Pin must be driven from a low jitter source. Since the

falling edge on the CONVST Pin determines the sampling instant,

any jitter that may exist on this edge will appear as noise when

the analog input signal contains high frequency components. The

relationship between the analog input frequency (fIN), timing

jitter (tj), and resulting SNR is given by the equation:

SNRJITTER

(dB) = 10log

(2π

×

1

fIN

× t j )2

As an example, if the desired SNR due to jitter was 100 dB with a

maximum full-scale analog input frequency of 1.5 MHz, ignor-

ing all other noise sources, the result is an allowable jitter on the

CONVST falling edge of 1.06 ps. For a 12-bit converter (ideal

SNR = 74 dB), the allowable jitter will be greater than the figure

given above, but due consideration must be given to the design

of the CONVST circuitry to achieve 12-bit performance with

large analog input frequencies.

–12–

REV. 0

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