AD7675 查看數據表（PDF） - Analog Devices

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AD7675

16-Bit, 100 kSPS, Differential ADC

Analog Devices 

AD7675

Table I. Serial Clock Timings in Master Read after Convert

DIVSCLK[1]

DIVSCLK[0]

0

0

1

0

1

0

SYNC to SCLK First Edge Delay Minimum t18

3

17

17

Internal SCLK Period Minimum

t19

25

50

100

Internal SCLK Period Typical

t19

40

70

140

Internal SCLK HIGH Minimum

t20

12

22

50

Internal SCLK LOW Minimum

t21

7

21

49

SDOUT Valid Setup Time Minimum

t22

4

18

18

SDOUT Valid Hold Time Minimum

t23

2

4

30

SCLK Last Edge to SYNC Delay Minimum

t24

3

60

140

Busy High Width Maximum

t28

2

2.5 3.5

1

1

Unit

17

ns

200 ns

280 ns

100 ns

99

ns

18

ns

89

ns

300 ns

5.75 µs

ABSOLUTE MAXIMUM RATINGS1

Analog Inputs

IN+2, IN–2, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ± 0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW

Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . 2.5 W

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150° C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2See Analog Input section.

3Specification is for device in free air: 48-Lead LQFP: ␪JA = 91°C/W, ␪JC = 30°C/W.

4Specification is for device in free air: LFCSP: ␪JA = 26°C/W

1.6mA IOL

TO OUTPUT

PIN CL

60pF1

1.4V

500␮A IOH

NOTE

1IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

Figure 1. Load Circuit for Digital Interface Timing, SDOUT,

SYNC, SCLK Outputs, CL = 10 pF

0.8V

tDELAY

2V

0.8V

2V

tDELAY

2V

0.8V

Figure 2. Voltage Reference Levels for Timing

ORDERING GUIDE

Model

Temperature Range Package Description

Package

Option

AD7675AST

AD7675ASTRL

AD7675ACP

AD7675ACPRL

EVAL-AD7675CB1

EVAL-CONTROL BRD22

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

Quad Flatpack (LQFP)

Quad Flatpack (LQFP)

Chip Scale (LFCSP)

Chip Scale (LFCSP)

Evaluation Board

Controller Board

ST-48

ST-48

CP-48

CP-48

NOTES

1This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/

demonstration purposes.

2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. A

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