ADP5020(RevA) 查看數據表（PDF） - Analog Devices

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ADP5020
(Rev.:RevA)

Power Management Unit for Imaging Modules

Analog Devices 

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADP5020

BOTTOM VIEW

(Not to Scale)

ADP5020

TOP VIEW

(Not to Scale)

ADP5020

VOUT1 15

VOUT1 14

VDD3 13

VOUT3 12

EN/GPIO 11

EXPOSED

PAD

1 PGND2

2 VOUT2

3 VDDA

4 AGND

5 SYNC

PGND2 15

VOUT2 14

VDDA 13

AGND 12

SYNC 11

EXPOSED

PAD

1 VOUT1

2 VOUT1

3 VDD3

4 VOUT3

5 EN/GPIO

NOTES

1. EXPOSED PAD SHOULD BE CONNECTED

TO PGND1 AND PGND2.

Figure 4. Pin Configuration (Bottom View)

NOTES

1. EXPOSED PAD SHOULD BE CONNECTED

TO PGND1 AND PGND2.

Figure 5. Pin Configuration (Top View)

Table 9. Pin Function Descriptions

Pin No. Mnemonic

Description

1

PGND2

Power Ground Buck 2.

2

VOUT2

Feedback Buck 2.

3

VDDA

Supply Voltage Internal Analog Circuit.

4

AGND

Analog Ground.

5

SYNC

Frequency Synchronization. Connect to an external 19.2 MHz or 9.6 MHz clock signal to synchronize the

internal oscillator.

6

DGND

Digital Ground.

7

SDA

I2C Data.

8

SCL

I2C Clock.

9

VDD_IO

Supply Voltage for Internal Logic Inputs/Outputs.

10

XSHTDN

Shutdown Output, Active Low.

11

EN/GPIO

After power-on reset, this pin is defined as enable (EN). To enable active high, the I2C command can program

this pin to be an output (GPIO). A weak pull-down resistor is enabled when the pin operates as EN.

12

VOUT3

Regulated Output Voltage from LDO.

13

VDD3

Supply Voltage LDO.

14, 15 VOUT1

Feedback/Driver Buck 1 Output.

16

PGND1

Power Ground Buck 1.

17

SW1

Switch Pin Buck 1.

18

VDD1

Supply Voltage Buck 1.

19

VDD2

Supply Voltage Buck 2.

20

SW2

Switch Pin Buck 2.

EPAD Exposed paddle Exposed pad should be connected to PGND1 and PGND2.

Rev. A | Page 9 of 28

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