ADV7123JST330(RevB) 查看數據表（PDF） - Analog Devices
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ADV7123JST330 Datasheet PDF : 20 Pages
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ADV7123
3.3 V DYNAMIC SPECIFICATIONS (VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 680 ⍀, CL = 10 pF. All specifications are
TA = 25؇C, unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Double-Ended Output
67
dBc
67
dBc
63
dBc
55
dBc
62
dBc
60
dBc
54
dBc
48
dBc
57
dBc
58
dBc
52
dBc
41
dBc
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Spurious-Free Dynamic Range within a Window
70
dBc
70
dBc
65
dBc
54
dBc
67
dBc
63
dBc
58
dBc
52
dBc
62
dBc
61
dBc
55
dBc
53
dBc
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
77
dBc
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span
73
dBc
fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span
64
dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
74
dBc
fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span
73
dBc
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span
60
dBc
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
TMIN to TMAX
fCLK = 50 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
66
dBc
65
dBc
64
dBc
64
dBc
55
dBc
DAC PERFORMANCE
Glitch Impulse
DAC Crosstalk3
Data Feedthrough4, 5
Clock Feedthrough4, 5
10
pVs
23
dB
22
dB
33
dB
NOTES
1These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
Specifications subject to change without notice.
REV. B
–5–
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