PALCE22V10-25DMB 查看數據表（PDF） - Cypress Semiconductor
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PALCE22V10-25DMB Datasheet PDF : 13 Pages
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PALCE22V10
]
Commercial Switching Characteristics PALCE22V10[2,7]
22V10-5
22V10-7 22V10-10 22V10-15 22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPD
Input to Output
Propagation Delay[8]
3
5
3 7.5 3 10 3 15 3 25 ns
tEA
Input to Output
Enable Delay[9]
6
8
10
15
25 ns
tER
Input to Output
Disable Delay[10]
6
8
10
15
25 ns
tCO
Clock to Output Delay[8]
2
4
2
5
2
7
2
8
2 15 ns
tS1
Input or Feedback Set-Up Time 3
5
6
10
15
ns
tS2
Synchronous Preset Set-Up
4
6
7
10
15
ns
Time
tH
tP
tWH
tWL
fMAX1
fMAX2
fMAX3
tCF
Input Hold Time
0
0
0
0
0
ns
External Clock Period (tCO + tS) 7
10
12
20
30
ns
Clock Width HIGH[6]
2.5
3
3
6
13
ns
Clock Width LOW[6]
2.5
3
3
6
13
ns
External Maximum
143
100
76.9
55.5
33.3
MHz
Frequency (1/(tCO + tS))[11]
Data Path Maximum Frequency 200
166
142
83.3
35.7
MHz
(1/(tWH + tWL))[6, 12]
Internal Feedback Maximum
181
133
111
68.9
38.5
MHz
Frequency (1/(tCF + tS))[6,13]
Register Clock to
Feedback Input[6,14]
2.5
2.5
3
4.5
13 ns
tAW
Asynchronous Reset Width
8
tAR
Asynchronous Reset
4
Recovery Time
8
10
15
25
ns
5
6
10
25
ns
tAP
Asynchronous Reset to
Registered Output Delay
7.5
12
13
20
25 ns
tSPR
Synchronous Preset
Recovery Time
4
6
8
10
15
ns
tPR
Power-Up Reset Time[6,15]
1
1
1
1
1
µs
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test
Loads and Waveforms is used for tEA(+).
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring
tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied
Document #: 38-03027 Rev. **
Page 6 of 13
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