PSD834F2-10JIT 查看數據表（PDF） - STMicroelectronics

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PSD834F2-10JIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

SRAM

The SRAM is enabled when SRAM Select (RS0) accesses the SRAM. Any address in the range of

from the DPLD is High. SRAM Select (RS0) can CSBOOT0 greater than 87FFh (and less than

contain up to two product terms, allowing flexible 9FFFh) automatically addresses secondary Flash

memory mapping.

memory segment 0. Any address greater than

SRAM Select (RS0) is configured using PSDsoft

Express Configuration.

Sector Select and SRAM Select

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)

and SRAM Select (RS0) are all outputs of the

DPLD. They are setup by writing equations for

them in PSDabel. The following rules apply to the

equations for these signals:

1. Primary Flash memory and secondary Flash

memory Sector Select signals must not be

larger than the physical sector size.

9FFFh accesses the primary Flash memory seg-

ment 0. You can see that half of the primary Flash

memory segment 0 and one-fourth of secondary

Flash memory segment 0 cannot be accessed in

this example. Also note that an equation that de-

fined FS1 to anywhere in the range of 8000h to

BFFFh would not be valid.

Figure 6 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level one has the highest priority and

2. Any primary Flash memory sector must not be

level 3 has the lowest.

mapped in the same memory space as another

Flash memory sector.

t(s) 3. A secondary Flash memory sector must not be

mapped in the same memory space as another

c secondary Flash memory sector.

u 4. SRAM, I/O, and Peripheral I/O spaces must not

d overlap.

ro 5. A secondary Flash memory sector may overlap

P a primary Flash memory sector. In case of

te overlap, priority is given to the secondary Flash

memory sector.

le 6. SRAM, I/O, and Peripheral I/O spaces may

o overlap any other memory sector. Priority is

bs given to the SRAM, I/O, or Peripheral I/O.

O Example. FS0 is valid when the address is in the

- range of 8000h to BFFFh, CSBOOT0 is valid from

) 8000h to 9FFFh, and RS0 is valid from 8000h to

Obsolete Product(s 87FFh. Any address in the range of RS0 always

Figure 6. Priority Level of Memory and I/O

Components

Highest Priority

Lowest Priority

Level 1

SRAM, I /O, or

Peripheral I /O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

AI02867D

23/95

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