PSD834F2-10JIT 查看數據表（PDF） - STMicroelectronics

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PSD834F2-10JIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

PLDS

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

using the PSDabel tool in PSDsoft Express, the

logic is programmed into the device and available

upon Power-up.

Additionally, five bits are available in PMMR2 to

block MCU control signals from entering the PLDs.

This reduces power consumption and can be used

only when these MCU control signals are not used

in PLD logic equations.

The PSD contains two PLDs: the Decode PLD Each of the two PLDs has unique characteristics

(DPLD), and the Complex PLD (CPLD). The PLDs suited for its applications. They are described in

are briefly discussed in the next few paragraphs, the following sections.

and in more detail in the section entitled “Decode

PLD (DPLD)”, on page 29, and the section entitled

“Complex PLD (CPLD)”, also on page 30. Figure

Table 12. DPLD and CPLD Inputs

10 shows the configuration of the PLDs.

Number

The DPLD performs address decoding for Select

signals for internal components, such as memory,

Input Source

Input Name

of

Signals

registers, and I/O ports.

MCU Address Bus1 A15-A0

16

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

MCU Control Signals CNTL2-CNTL0

3

chines, and encoding and decoding logic. These

) logic functions can be constructed using the 16

t(s Output Macrocells (OMC), 24 Input Macrocells

(IMC), and the AND Array. The CPLD can also be

c used to generate External Chip Select (ECS0-

u ECS2) signals.

rod The AND Array is used to form product terms.

These product terms are specified using PSDabel.

P An Input Bus consisting of 73 signals is connected

te to the PLDs. The signals are shown in Table 12.

le The Turbo Bit in PSD

o The PLDs in the PSD can minimize power con-

s sumption by switching off when inputs remain un-

b changed for an extended time of about 70ns.

O Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) au-

- tomatically places the PLDs into standby if no in-

) puts are changing. Turning the Turbo mode off

t(s increases propagation delays while reducing pow-

er consumption. See the section entitled “POWER

c MANAGEMENT”, on page 56, on how to set the

Obsolete Produ Turbo Bit.

Reset

RST

1

Power-down

PDN

1

Port A Input

Macrocells

PA7-PA0

8

Port B Input

Macrocells

PB7-PB0

8

Port C Input

Macrocells

PC7-PC0

8

Port D Inputs

PD2-PD0

3

Page Register

PGR7-PGR0

8

Macrocell AB

Feedback

MCELLAB.FB7-

FB0

8

Macrocell BC

Feedback

MCELLBC.FB7-

FB0

8

Secondary Flash

memory Program

Ready/Busy

1

Status Bit

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

27/95

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