GMS30C2116 查看數據表（PDF） - Hynix Semiconductor

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GMS30C2116

16/32 BIT RISC/DSP

Hynix Semiconductor 

0-6

0.2 Block Diagram

CHAPTER 0

Register Set

64 Local

26 Global

X Y PC

X-Decode

Y-Decode

Instruction

Cache

Control

Instruction

Cache

Load

Decode

Instruction

Decode

XY I

ALU

Barrel shifter

ZW A

Store Data

Pipeline

XY

DSP

Execution

Unit

Hardware-

Multiplier

Instruction

Execution

Control Unit

Instruction Prefetch

Control Unit

Memory Address

Pipeline

Bus Interface

Control Unit

Bus Pipeline

Control

32

4

(16)

(2)

Data Bus Parity

32 12

26

(22)

4 kByte

RAM

Address

Bus

Watchdog

Power

Down+

Reset

Control

Internal

Timer

Interrupt

control

4

Control

Bus

Figure 0.1: Block Diagram

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