UAA3202 查看數據表（PDF） - Philips Electronics

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UAA3202

Frequency Shift Keying (FSK) receiver

Philips Electronics 

Philips Semiconductors

Frequency Shift Keying (FSK) receiver

Preliminary specification

UAA3202M

TEST INFORMATION

Tuning procedure for AC tests

1. Turn on the signal generator (fi = 433.92 MHz; no modulation; RF input level = −60 dBm).

2. Tune C6 (RF stage input) to obtain a peak voltage on test point A (see Fig.11).

3. Turn on modulation (fi = 433.92 MHz; fmod = 250 Hz square wave; ∆f = 25 kHz; RF input level = −60 dBm).

4. Check that data is appearing on the data output (pin 11) and proceed with the AC tests.

AC test conditions

Table 2 Test signals

The reference signal level Pref for the following tests is defined as the minimum input level in dBm to give a

BER ≤ 3 × 10−2 (e.g. 15 bit errors per second for 500 bits/s).

TEST

SIGNAL

1

2

3

FREQUENCY

(MHz)

433.92

433.92

433.82

DATA SIGNAL

250 Hz square wave

−

−

MODULATION

FM (FSK)

no modulation

no modulation

FREQUENCY

DEVIATION

25 kHz

−

−

Table 3 Test results

P1 is the maximum available power from signal generator 1 at the input of the test board; P2 is the maximum available

power from signal generator 2 at the input of the test board.

TEST

Sensitivity into pin MXIN

(see Fig.6)

Maximum input power

(see Fig.6)

Receiver turn-on time; note 1

Intercept point (mixer + PMA)

see note 2 and Fig.7

Spurious radiation see note 3

and Fig.8

1 dB compression point

(mixer + PMA) see note 2

and Fig.9

GENERATOR

1

2

modulated test

−

signal 1; P1 ≤ −94 dBm

modulated test

−

signal 1; P1 ≥ −30 dBm

(minimum Pmax)

test signal 1;

−

P1 = Pref + 10 dB

test signal 3;

P1 = −55 dBm

−

test signal 2;

P2 = P1

−

test signal 3;

−

P11 = −70 dBm;

P12 = −45 dBm

(minimum P1dB)

RESULT

BER ≤ 3 × 10−2

(e.g. 15 bit errors per second for 500 bits/s)

BER ≤ 3 × 10−2

(e.g. 15 bit errors per second for 500 bits/s)

check that the first 10 bits are correct; error

counting is started 10 ms after PWD

switched to operating mode: ON

IP3 = P1 + 1⁄2 × IM3 (dB); IP3 ≥ −38 dBm

no spurious radiation (25 MHz − 1 GHz)

with level higher than −60 dBm

(maximum Pspur)

(Po1 + 70 dB) − [Po2 + 45 dB (minimum

P1 dB)] ≤ 1 dB, where Po1, Po2 is the output

power for test signals with P11 or P12,

respectively

Notes

1. The power-down voltage VPWD alternates between operating mode ON (100 ms) and OFF (100 ms); see Fig.5.

2. Probe of spectrum analyzer connected to test point A.

3. Spectrum analyzer connected to the input of the test board.

1997 Aug 12

14

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