HYS64V2200GU-8 查看數據表（PDF） - Siemens AG

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HYS64V2200GU-8

3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module

Siemens AG 

HYS64(72)V2200/4220GU-8/-10

SDRAM-Modules

SPD-Table (contd’ ):

Byte#

Description

29 Minimum RAS to CAS delay tRCD

30 Minimum RAS pulse width tRAS

31 Module Bank Density (per bank)

32 SDRAM input setup time

33 SDRAM input hold time

34 SDRAM data input setup time

35 SDRAM data input hold time

36-61 Superset information (may be used in

future)

62 SPD Revision

63 Checksum for bytes 0 - 62

64- Manufacturers information (optional)

125 (FFh if not used)

126 Frequency Specification

127 Details

128+ Unused storage locations

SPD Entry Value

30 ns

45 ns

16 MByte

3 ns

1 ns

3 ns

1 ns

Hex

2Mx64 2Mx72 4Mx64 4Mx72

-10 -10 -10 -10

1E

1E

1E

1E

2D

2D

2D

2D

04

04

04

04

30

30

30

30

10

10

10

10

30

30

30

30

10

10

10

10

FF

FF

FF

FF

Revision 1.2

12

12

12

12

A1

B3

A2

B4

XX XX XX XX

66 MHz

66

66

66

66

AF

AF

FF

FF

FF

FF

FF

FF

Semiconductor Group

16

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