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HYS64V2200GU-10 查看數據表(PDF) - Siemens AG
零件编号
产品描述 (功能)
生产厂家
HYS64V2200GU-10
3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
Siemens AG
HYS64V2200GU-10 Datasheet PDF : 17 Pages
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HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
AC Characteristics
3)4)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
-8
PC100
2-2-2
-8-3
PC100
3-2-3
-10
PC66
2-2-2
min. max. min. max. min. max.
Note
Clock and Clock Enable
Clock Cycle Time
t
CK
CAS Latency = 3
CAS Latency = 2
System Frequency
f
CK
CAS Latency = 3
CAS Latency = 2
Clock Access Time
t
AC
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Input Setup time
Input Hold Time
CKE Setup Time
(Power down mode)
t
CH
t
CL
t
CS
t
CH
t
CKSP
CKE Setup Time
(Self Refresh Exit)
t
CKSR
Transition time (rise and fall)
t
T
Common Parameters
RAS to CAS delay
t
RCD
Cycle Time
t
RC
Active Command Period
t
RAS
Precharge Time
t
RP
Bank to Bank Delay Time
t
RRD
CAS to CAS delay time
t
CCD
(same bank)
10
10
10
ns
10
10
15
ns
– 100 – 100 – 100 MHz
– 100 – 100 – 66 MHz
–
6
–
6
–
8 ns
4,5)
–
6
–
7
–
9 ns
3
–
3
– 3.5 – ns
6)
3
–
3
– 3.5 – ns
6)
2
–
2
–
3
– ns
7)
1
–
1
–
1
– ns
7)
2.5 – 2.5 –
3
– ns
8)
8
–
8
–
8
– ns
9)
1
–
1
–
1
– ns
20 – 20 – 30 – ns
70 120k 70 120k 75 120k ns
45 – 45 – 45 – ns
20 – 30 – 30 – ns
16 – 20 – 20 – ns
1
–
1
–
1
– CLK
Semiconductor Group
8
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