LP61L1008 查看數據表（PDF） - AMIC Technology
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LP61L1008 Datasheet PDF : 13 Pages
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LP61L1008 Series
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
General Description
n Single 3.3V ± 10% power supply
n Access times: 12/15 ns (max.)
n Current: Operating: 180mA (max.)
Standby: 5mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
n Center Power/Ground Pin Configuration
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2.0V (min.)
n Available in 32-pin SOJ 300 mil and 32-pin sTSOP
packages
The LP61L1008 is a high speed 1,048,576-bit static
random access memory organized as 131,072
words by 8 bits and operates on a single 3.3V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Product Family
Product
Family
Operating
Temperature
VCC
Range
Speed
Power Dissipation
Data Retention Standby Operating
(ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.)
LP61L1008
0°C~70°C 3.0V~3.6V 12/15 ns
10µA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
20µA
66mA
Package
Type
32L SOJ
32L sTSOP
Pin Configuration
n SOJ
n sTSOP
A0
1
A1
2
A2
3
A3
4
CE
5
I/O1
6
I/O2
7
VCC
8
GND
9
I/O3
10
I/O4
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 A16
31
A15
30
A14
29
A13
28
OE
27
I/O8
26
I/O7
25
GND
24
VCC
23
I/O6
22
I/O5
21
A12
20 A11
19 A10
18 A9
17 A8
A0
1
A1
2
A2
3
A3
4
CE
5
I/O0
6
I/O1
7
VCC
8
VSS
9
I/O2
10
I/O3
11
WE
12
A4
13
A5
14
A6
15
A7
16
LP61L1008X
32
A16
31
A15
30
A14
29
A13
28
OE
27
I/O7
26
I/O6
25
VSS
24
VCC
23
I/O5
22
I/O4
21
A12
20
A11
19
A10
18
A9
17
A8
(June, 2002, Version 2.0)
1
AMIC Technology, Inc.
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