LPC2104FBD48/01 查看數據表（PDF） - NXP Semiconductors.

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LPC2104FBD48/01

Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM

NXP Semiconductors. 

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

• Standard modem interface signals included on UART 1.

6.10.2 UART features available in LPC2104/2105/2106/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01

introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers

to achieve standard baud rates such as 115200 Bd with any crystal frequency above

2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in

hardware.

• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be

achieved with any crystal frequency above 2 MHz.

• Autobauding.

• Auto-CTS/RTS flow-control fully implemented in hardware.

6.11 I2C-bus serial I/O controller

I2C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL),

and a serial data line (SDA). Each device is recognized by a unique address and can

operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast

I2C-bus).

6.11.1 Features

• Standard I2C compliant bus interface.

• Easy to configure as Master, Slave or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus may be used for test and diagnostic purposes.

LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

© NXP B.V. 2008. All rights reserved.

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