M62362P(2007) 查看數據表（PDF） - Renesas Electronics
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M62362P Datasheet PDF : 11 Pages
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M62362P/FP
Digital Data Format
Last
First
LSB
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
DAC data
DAC select
data
DAC Data
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
D/A Output
0
0
0
0
0
0
0
0
0
0
0
VDAref
1
0
0
0
0
0
0
0
0
0
0 (VIN – VDAref) / 1280 × 1 + VDAref
0
1
0
0
0
0
0
0
0
0
0 (VIN – VDAref) / 1280 × 2 + VDAref
1
1
0
0
0
0
0
0
0
0
0 (VIN – VDAref) / 1280 × 3 + VDAref
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
0
0
1 (VIN – VDAref) / 1280 × 1279 + VDAref
0
0
0
0
0
0
0
0
1
0
1 VIN
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1 VIN
DAC Select Data
D11
0
0
1
1
D12
0
Don't care
1
ch1
0
ch2
1
ch3
DAC Selection
Timing Chart (Model)
MSB
DI
D12
D11
D10
.............
LSB
D1
D0
CLK
BS
RESET
.............
D/A
output
Note: Input data is carried out BS signal "L" besides CLK signal positive edge. CLK, BS, is keep generally
"H" level.
REJ03D0873-0201 Rev.2.01 Dec 27, 2007
Page 6 of 10
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