MU9C8148 查看數據表（PDF） - Music Semiconductors

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MU9C8148

SRT Interface

Music Semiconductors 

MU9C8148

REGISTER SET DESCRIPTION (CONT’D)

BIT NAME

DESCRIPTION

Second Access

15–8 DTE7–0

7–0 LIDM7–0

Third Access

15–8 ALIM7–0

7–0 SLIM7–0

DTE7–0 contain the value of the DUPLANIDORTREEERROR counter, which totals the number of STE

frames that were discarded because the pre-stored LOUT already exists in the RIF. After readout this

error counter is reset to 00H.

LIDM7–0 contain the value of the LAN ID MISMATCH counter, which totals the number of ARE and STE

frames that were discarded because the last LAN ID in the RIF did not equal the preset LIN. After

readout this error counter is reset to 00H.

ALIM7–0 contain the value of the ARERDLIMIT EXCEEDED counter, which totals the number of ARE

frames discarded due to ARERD Limit exceeded. After readout this error counter is reset to 00H.

SLIM7–0 contain the value of the STERDLIMIT EXCEEDED counter, which totals the number of STE

frames discarded due to STERD Limit exceeded. After readout this error counter is reset to 00H.

18H: LANCAM CWEC Register

15–0 CWEC15–0

Writing to this register starts a direct LANCAM access whereby the data written to CWEC15–0 is placed

on the DQ15–0 lines and /W, /CM and /EC are held LOW. This register should not be used while

routines are enabled.

19H: LANCAM CREC Register

15–0 CREC15–0

Reading from this register starts a direct LANCAM access whereby the data read from CREC15–0 is

data placed on the DQ15–0 lines by the LANCAM. /CM and /EC are held LOW and /W is held HIGH for

this LANCAM cycle. This register should not be used while routines are enabled.

1AH: LANCAM DWEC Register

15–0 DWEC15–0

Writing to this register starts a direct LANCAM access whereby the data written to DWEC15–0 is placed

on the DQ15–0 lines and /W and /EC are held LOW while /CM is held HIGH for this LANCAM cycle.

This register should not be used while routines are enabled.

1BH: LANCAM DREC Register

15–0 DREC15–0

Reading from this register starts a direct LANCAM access whereby the data read from DREC15–0 is

data placed on the DQ15–0 lines by the LANCAM. /EC is held LOW and /W and /CM are held HIGH for

this LANCAM cycle. This register should not be used while routines are enabled.

1CH: LANCAM CWNEC Register

15–0 CWEC15–0

Writing to this register starts a direct LANCAM access whereby the data written to CWNEC15–0 is

placed on the DQ15–0 lines and /W and /CM are held LOW while /EC is held HIGH for this LANCAM

cycle. This register should not be used while routines are enabled.

1DH: LANCAM CRNEC Register

15–0 CRNEC15–0

Reading from this register starts a direct LANCAM access whereby the data read from CRNEC15–0 is

data placed on the DQ15–0 lines by the LANCAM. /CM is held LOW and /W and /EC are held HIGH for

this LANCAM cycle. This register should not be used while routines are enabled.

1EH: LANCAM DWNEC Register

15–0 DWNEC15–0

Writing to this register starts a direct LANCAM access whereby the data written to DWNEC15–0 is

placed on the DQ15–0 lines and /W is held LOW while /CM and /EC are held HIGH for this LANCAM

cycle. This register should not be used while routines are enabled.

1FH: LANCAM DRNEC Register

15–0 DRNEC15–0

Reading from this register starts a direct LANCAM access whereby the data read from DRNEC15–0 is

data placed on the DQ15–0 lines by the LANCAM. /EC, /W and /CM are held HIGH for this LANCAM

cycle. This register should not be used while routines are enabled.

Rev. 5.5 Draft web

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