P2V28S20ATP-7 查看數據表（PDF） - Vanguard International Semiconductor

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P2V28S20ATP-7

128Mb SDRAM Specification

Vanguard International Semiconductor 

128Mb Synchronous DRAM

P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)

P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)

P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)

BURST INTERRUPTION [ Read Interrupted by Read ]

Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval

is minimum 1 CLK..

Read Interrupted by Read (BL=4, CL=3)

CLK

Command

A0-9

A10

A11

BA0,1

DQ

READ READ

Yi Yj

00

READ

Yk

0

0

READ

Yl

00 00

10

01

Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3

[ Read Interrupted by Write ]

Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ

should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1

cycle after WRITE assertion.

Read Interrupted by Write (BL=4, CL=3)

CLK

Command

A0-9

A10

A11

BA0,1

DQM

Q

D

READ

Yi

0

00

Write

Yj

0

00

Qai0

Daj0 Daj1 Daj2 Daj3

DQM control Write control

JULY.2000

Page-20

Rev.2.2

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