RH56D-PCI 查看數據表（PDF） - Unspecified
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RH56D-PCI Datasheet PDF : 60 Pages
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Label
XIN
XOUT
VDD
AVDD
GND
AGND
AGNDM
AGNDV
SET3V#
VIO
VIO
CLKRUN#
VauxEN#
VpciEN#
VpciDET
SROMCLK
SROMCS
SROMIN
SROMOUT
RH56D-PCI Modem Designer’s Guide
Pin
83
82
2, 7, 20, 25, 30,
34, 40, 71, 79,
81, 97, 105,
115, 135
59
35, 84, 98, 113,
141, 142, 143
54, 55, 70, 78
67
57
80
1
140
129
116
117
125
122
119
121
120
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I/O Type
Signal Name/Description
SYSTEM
It, Ot2
Crystal In and Crystal Out. Connect XIN and XOUT to a 28.224000 MHz external
crystal circuit.
PWR
Digital Supply Voltage. Connect to +3.3V.
PWR
GND
Analog Circuits Digital Power. Connect to Analog IA power.
Digital Ground. Connect to digital ground.
GND
GND
GND
It
PWR
Ip,
(in, o/d,
s/t/s)
Ot2
Ot2
Itpd
Ot4
Ot2
Ot4
Itpu
Analog Ground. Connect to analog ground.
Analog Ground Modem. Connect to analog ground.
Analog Ground Voice. Connect to analog ground.
Select 3.3V Analog Voltage Reference. Low selects +3.3V analog voltage reference;
high selects +5V analog voltage reference
I/O Signaling Voltage Source. Connect to PCI Bus VI/O. Used internally for PCI
clamping.
Clock Running. CLKRUN# is an input used to determine the status of CLK and an
open drain output used to request starting or speeding up CLK. Connect to GND for
PCI designs. May be connected to GND through 1KΩ but resistor is not required.
POWER DETECTION AND SWITCHING
Vaux Enable. Active low output used to enable Vaux FET. For use in designs that
switch between Vaux and Vpci for different power states and for retail designs where
the target PC may or may not support Vaux. If used, tie to the gate of the P-FET
connected between Vaux and board +3.3V grid. If not used, leave open.
Vpci Enable. Active low output used to enable Vpci FET. For use in designs that
switch between Vaux and Vpci for different power states and for retail designs where
the target PC may or may not support Vaux. If used, tie to the gate of the P-FET
connected between Vpci regulator output and board +3.3V grid. If not used, leave
open.
Vpci Detect. The VpciDET input indicates when PCI cycles and PCIRST# are to be
ignored. Connect this pin to the PCI Bus +5V pins. VpciDET is deasserted when the
PCI Bus enters the B3 state. If the +5V supply does not fall below 0.8V when in B3
state, a diode and resistor network may be incorporated to ensure VpciDET falls below
0.8V in order to be properly sensed by the BIF.
This pin may alternatively be directly driven in embedded designs by using a logical
signal, either +5V or +3.3V level, to indicate when the PCI Bus is in a B3 state. Driving
this pin low synchronously to the PCI clock or when the PCI clock is stopped also
allows the BIF to be put into a very low power mode, allowing system power
consumption to be less than 20 mW. Therefore, using this method, if modem operation
is not required, modem power consumption can be reduced even while the PCI Bus is
in power state B0.
SERIAL EEPROM INTERFACE
Serial ROM Shift Clock. Connect to SROM SK input (frequency: 537.6 kHz).
Serial ROM Chip Select. Connect to SROM CS input.
Serial ROM Instruction, Address, and Data In. Connect to SROM DI input.
Serial ROM Device Status and Data Out. Connect to SROM DO output, through
1k Ω if using a +5V EEPROM.
1213
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