S29AL004D 查看數據表（PDF） - Spansion Inc.

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S29AL004D

4 Megabit (512 Kx 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Spansion Inc. 

Advance Information

is in the standby mode, but the standby current is greater. The device requires

standard access time (tCE) for read access when the device is in either of these

standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

In the iDC Characteristics table, ICC3 and ICC4 represents the standby current

specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for tACC + 30

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new data when addresses are

changed. While in sleep mode, output data is latched and always available to the

system. ICC4 in the iDC Characteristics table represents the automatic sleep mode

current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a 0 (busy) until the internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing (RY/BY# pin is 1), the reset

operation is completed within a time of tREADY (not during Embedded Algorithms).

The system can read data tRH after the RESET# pin returns to VIH.

Refer to the tables AC Characteristics‚ on page 37 for RESET# parameters and

to Figure 14, on page 38 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins

are placed in the high impedance state.

Table 2. S29AL004D Top Boot Block Sector Addresses (Sheet 1 of 2)

Sector A17 A16 A15 A14 A13

SA0

0

0

0

X

X

Sector Size

(Kbytes/

A12 Kwords)

X

64/32

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

Address Range

00000h–0FFFFh 00000h–07FFFh

February 18, 2005 S29AL004D_00_A1

S29AL004D

13

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