S3067 查看數據表（PDF） - Unspecified
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S3067 Datasheet PDF : 27 Pages
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 20. Transmitter AC Timing Characteristics
Parameter
Description
TSCLK Frequency
BYPASS Clock Frequency
TSCLK Duty Cycle
TSCLK Duty Cycle Distortion w.r.t. RSCLK or
BYPASSCLK (In SLPTIME, LLEB or BYPASS modes)
PICLK Duty Cycle
tSPIN
tHPIN
tPCLK
tSTSD
tHTSD
PIN [15:0] Set-up Time w.r.t. PICLK (See Figure 9)
PIN [15:0] Hold Time w.r.t. PICLK (See Figure 9)
PCLK to PICLK drift after the FIFO is centered
TSD Set-up Time w.r.t. TSCLK Rising (See Figure 9)
TSD Hold Time w.r.t. TSCLK Rising (See Figure 9)
PCLKP/N Duty Cycle
Min
Max
Units
2.7
GHz
2.7
GHz
43
57
%
5.0
%
35
65
%
1.5
ns
0.5
ns
5.2
ns
100
ps
100
ps
45
55
%
Figure 9. Transmitter Input Timing1
Figure 10. Transmitter Output Timing1
PICLKP
PIN[15:0]
tSPIN
tHPIN
TSCLKP
TSD
tSTSD
tHTSD
Notes on High-Speed Timing:
1. Timing is measured from the cross-over point of the reference signal to the 50% level of the input/output.
20
September 17, 2002/ Revision A
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