T35L6464A 查看數據表（PDF） - Taiwan Memory Technology

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产品描述 (功能)

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T35L6464A

SYNCHRONOUS BURST SRAM 64K x 64 SRAM

Taiwan Memory Technology 

tm TE

CH

READ/WRITE TIMING

C LK

t KC

t KH t KL

t A DS S t A DS H

A DSP

T35L6464A

ADS C

A D D R E S S A1

t AS t AH

A2

B W 1 -B W 8

CE

(N O T E 2 )

t C ES t C EH

A3

A4

t WS t WH

A5

A6

ADV

OE

t KQ

t DS t DH

tO ELZ

D

Hig h-Z

D (A3)

D (A5)

D (A6)

t KQLZ

tO E HZ

tK Q

(NO TE 1)

Q

Hig h-Z

Q (A1 )

Q (A2 )

Q (A3 )

Q (A 4)

Q(A 4+1

)

Q (A4 +2) Q(A 4+3 )

B ac k-to-B ac k RE A Ds

Si ng le WR IT E

P as s -throu gh

READ

BU RST RE AD

B ac k-to-B ac k

WRIT E s

DO N' T C ARE

UN DEF INED

Note: 1. Q (A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst

address following A4.

2. CE2 , CE2, CE3 and CE3 have timing identical to CE . On this diagram, when CE is LOW,

CE2 , CE3 is LOW and CE2, CE3 is HIGH. When CE is HIGH, CE2 , CE3 is HIGH and CE2,

CE3 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or

ADV cycle is performed.

4. GW is HIGH.

5. Back-to-back READs may be controlled by either ADSP or ADSC .

Taiwan Memory Technology, Inc. reserves the right P. 14

to change products or specifications without notice.

Publication Date: AUG. 1998

Revision: E

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