T5760 / T5761
Digital Signal Processing
The data from the ASK/ FSK demodulator (Dem_out) is
digitally processed in different ways and as a result con-
verted into the output signal data. This processing
depends on the selected baud-rate range (BR_Range).
Figure 14 illustrates how Dem_out is synchronized by the
extended clock cycle TXClk. This clock is also used for the
bit-check counter. Data can change its state only after
TXClk has elapsed. The edge-to-edge time period tee of the
Data signal as a result is always an integral multiple of
TXClk.
The minimum time period between two edges of the data
TXClk
signal is limited to tee ≥ TDATA_min. This implies an effi-
cient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at
DATA. This eases the interrupt handling of a connected
µC.
The maximum time period for DATA to stay Low is lim-
ited to TDATA_L_max. This function is employed to ensure
a finite response time in programming or switching off the
receiver via Pin DATA. TDATA_L_max is thereby longer
than the maximum time period indicated by the transmit-
ter data stream. Figure 16 gives an example where
Dem_out remains Low after the receiver has switched to
receiving mode.
Clock bit–check
counter
Dem_out
Data_out (DATA)
tee
Figure 14. Synchronization of the demodulator output
Dem_out
Data_out (DATA)
tDATA_min
tee
tDATA_min
tee
tDATA_min
tee
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
Start–up mode
Figure 15. Debouncing of the demodulator output
Bit–check mode
tDATA_min
Receiving mode
tDATA_L_max
Figure 16. Steady L state limited DATA output pattern after transmission
Rev. A2, 19-Oct-00
Preliminary Information
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