V96BMC 查看數據表（PDF） - Unspecified

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V96BMC

HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx® PROCESSORS

Unspecified 

ALE

A(31:2)

Figure 4: ALE Timing

TALE

V96BMC Rev.D

ADDRESS

TASU

TAH

PCLK

ADS

ADDR

W/R

BLAST

READY

Ax11:0

RASx

CASx

MWEx

Figure 5: Basic Access Timing

0

1

2

3

4

5

6

7

8

Address N

tRZH

tARA2

tRHL

tRAH

Row

tCAV

tWESU

tRCD

tRHL

tCAH

Col

tRAS

tCHL

tRLH

tCLH

tCAS

tRLH tRHZ

tRP

tWEH

tCPN

Copyright © 1998, V3 Semiconductor Corp.

V96BMC Rev D Data Sheet Rev 3.2

13

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