VG26S17405J 查看數據表（PDF） - Vanguard International Semiconductor
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VG26S17405J Datasheet PDF : 27 Pages
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VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Refresh Cycle
Parameter
CAS setup time (CBR refresh)
CAS hold time (CBR refresh)
RAS precharge to CAS hold time
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (CBR self refresh)
WE setup time
WE hold time
Symbol
tCSR
tCHR
tRPC
tRASS
tRPS
tCHS
tWSR
tWHR
VG26(V)(S)17405
-5
-6
Min Max Min Max Unit
5
-
5
- ns
8
-
10
- ns
5
-
5
- ns
100
- 100
- µs
90
- 110
- ns
-50
- -50
- ns
0
-
0
- ns
10
-
10
- ns
Notes
10
7
EDO Page Mode Cycle
Parameter
EDO page mode cycle time
EDO page mode CAS precharge time
EDO page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
OE high hold time from CAS high
OE high pulse width
Data output hold time after CAS low
Output disable delay from WE
WE pulse width for output disable when
CAS high
Symbol
tPC
tCP
tRASP
tCPA
tCPRH
tOEHC
tOEP
tCOH
tWHZ
tWPZ
VG26(V)(S) 17405
-5
-6
Min Max Min Max Unit Notes
20
- 25
- ns
10
- 10
- ns
50 105
- 30
60 105 ns
20
- 35 ns 10, 14
30
- 35
- ns
5
-
5
- ns
10
- 10
- ns
4
-
4
- ns
3 10
3 10 ns
7
-
7
- ns
Document:1G5-0162
Rev.1
Page 12
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