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TDA16888

High Performance Power Combi Controller

Infineon Technologies 

TDA 16888

The oscillator can be synchronized with an external clock signal supplied at pin 12

(SYNC). As long as this clock signal is H the oscillator’s triangular signal VOSC is

interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However,

as soon as the external clock changes from H to L the oscillator is released.

Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the

oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on

principle only within the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the

falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead

the lower voltage peak is modulated. Consequently, on the one hand at high

synchronization frequencies fSYNC > fOSC the amplitude of the ramp signal and

correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand

at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the

minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which

may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops

below this threshold. However, if the oscillator has to be synchronized over a wide

frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has

to be preferred to a synchronization by means of pin 12 (SYNC).

In order to reduce the overall current consumption under low load conditions, the

oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less

than 0.4 V (disabled PWM section).

Multiplier

The multiplier serves to provide the controlled current IQM by combination of the shape

of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means

of the 10 kΩ resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18

(PFC VC) and the possibility for soft overvoltage protection VM3 (see Chapter

Protection Circuitry). By means of this current the required power factor as well as the

magnitude of the PFC output voltage is ensured. To achieve an excellent performance

over a wide range of output power and input voltage, the input voltage VM2 is amplified

by an exponential function before being fed into the multiplier (see Figure 8).

Voltage Amplifier OP1

Being part of the outer loop the error amplifier OP1 controls the magnitude of the PFC

output voltage by comparison of the PFC output voltage measured at pin 17 (PFC FB)

with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity

from external noise. To allow for individual feedback the output of OP1 is connected to

pin 18 (PFC VC).

Data Sheet

11

2000-02-28

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