V380SDC 查看數據表（PDF） - QuickLogic Corporation

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V380SDC

High Performance SDRAM Controller for 32-bit and 64-bit Embedded Processors

QuickLogic Corporation 

Getting Help from V3 Semiconductor

Serial EEPROM Port Timings

5.1 Serial EEPROM Port Timings

The clock for the serial EEPROM interface is derived by dividing the processor bus clock. The waveforms generated

are shown in Figure 5.

Figure 5: Serial EEPROM Waveforms and Timings

START CONDITION

512 BUS

CLOCKS

STOP CONDITION

SCL

SDA

256 BUS

CLOCKS

256 BUS

CLOCKS

6.0 Getting Help from V3 Semiconductor

If you need assistance with a technical question, please contact us. E-mail is the quickest and most efficient way to

get technical support from V3.

Corporate Office

250 Consumers Road, Suite 901

Toronto, Ontario, Canada

M2J 4V6

Telephone:

1-877-283-7364

(416) 497-8884

Fax:

(416) 497-1160

E-mail:

V3help@vcubed.com

Sales Office

2348G Walsh Avenue

Santa Clara, California 95051

USA

Telephone:

1-800-488-8410

(408) 988-1050

Fax:

(408) 988-2601

Some technical support information is also posted on the V3 Web site. This is the source of the most up-to-date

documentation and is located at: http://www.vcubed.com.

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V380SDC_A0 Datasheet Rev 1.01 DS-SD01-0101

© 2000 V3 Semiconductor Corp.

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