HCF4521B 查看數據表（PDF） - STMicroelectronics

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HCF4521B

24 STAGE FREQUENCY DIVIDER

STMicroelectronics 

HCF4521B

FUNCTIONAL TEST SEQUENCE

INPUTS

RESET

IN 2

OUT

OUTPUTS

VSS1

VDD1

Q18 - Q24

COMMENTS

Counter is in three 8-stage

sections in parallel mode

H

L

L

VDD

VSS

L

Counter in reset. IN 2 and

OUT 2 are tied together

L

H

H

VDD

VSS

L

First LOW-to-HIGH transition

at IN 2

L

L

L

VDD

VSS

L

255 LOW-to-HIGH transition

L

H

H

VDD

VSS

L

are clocked in at IN 2

The 255th LOW-to-HIGH

L

H

H

VDD

VSS

H

transition

L

L

L

VDD

VSS

H

L

L

L

VSS

VSS

H

L

H

L

VSS

VDD

H

Counter Converted Back to

24-Stage in Series Mode

L

H

L

VSS

VDD

H

OUT 2 reverts to output opera-

tion

Counter ripples from an

L

L

H

VSS

VDD

L

all-HIGH state to an all-LOW

state

A test function (see Functional Test Circuit) has been included for the reduction of test time required to exercise all 24 counter stages. This

test function divides the counter into three 8-stage sections and 255 counts are loaded in each of the 8-stage sections in parallel. All flip-flop

are now at a logic "1". The counter in now returned to the normal 24-stages in series configuration. One more pulse is entered into Input 2

(In2) which will cause the counter to ripple from an all "1" state to an all "0" state.

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