M34C00 查看數據表（PDF） - STMicroelectronics
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M34C00 Datasheet PDF : 15 Pages
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M34C00
Figure 4. I2C Bus Protocol
SCL
SDA
START
Condition
SDA
Input
SDA
Change
STOP
Condition
SCL
SDA
1
2
3
MSB
START
Condition
7
8
9
ACK
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
Condition
AI00792B
must change only when Serial Clock (SCL) is
driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the 8-bit byte, shown in Table 3, on Serial
Data (SDA) (most significant bit first). This
consists of the 7-bit Device Select code, and the
Read/Write bit (RW).
To address the memory array, the 4-bit Device
Type Identifier is 1010b. To address the Protection
Register, it is 0110b, as shown in Table 3.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations. If a
match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Memory Partitioning
The memory is divided in three arrays:
s Array-0: Write-protectable Array (00h to 0Fh)
s Array-1: EEPROM Array (10h to 1Fh)
s Array-2: Non-Erasable Memory Array (20h to
2Fh)
The 4 least significant bits of the address byte
determine the byte that is to be addressed within
the given array. The next 2 more significant
address bits determine the array that is to be
addressed (Array-0, Array-1, Array-2 or Invalid).
The 2 most significant address bits are Don’t Care.
If the address is of the form xx11xxxx, the device
recognises that an attempt is being made to
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