70FL256P0XMFI00 查看數據表（PDF） - Cypress Semiconductor
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70FL256P0XMFI00 Datasheet PDF : 16 Pages
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S70FL256P
256-Mbit 3.0V Flash
This product is not recommended for new and current designs. For new and current designs, the S25FL256S supersedes S70FL256P. This is the
factory-recommended migration path. Refer to the S25FL256S datasheet for specifications and ordering information, and AN98592 for changes
required to migrate from existing designs based on S70FL256P.
Distinctive Characteristics
Architectural Advantages
One-time programmable (OTP) area on each Flash die for
Single Power Supply Operation
permanent, secure identification; can be programmed and
– Full voltage range: 2.7 to 3.6V read and write operations
locked at the factory or by the customer
Memory Architecture
n – Uniform 64 kB sectors
ig – Top or bottom parameter block (Two 64-kB sectors
broken down into sixteen 4-kB sub-sectors each) for
s each Flash die
e – Uniform 256 kB sectors (no 4-kB sub-sectors)
D – 256-byte page size
Program
w – Page Program (up to 256 bytes) in 1.5 ms (typical)
e – Program operations are on a page by page basis
N – Accelerated programming mode via 9V W#/ACC pin
r – Quad Page Programming
fo Erase
– Bulk erase function for each Flash die
– Sector erase (SE) command (D8h) for 64 kB and 256 kB
d sectors
e – Sub-sector erase (P4E) command (20h) for 4 kB sectors
d (for uniform 64-kB sector device only)
n – Sub-sector erase (P8E) command (40h) for 8 kB sectors
e (for uniform 64-kB sector device only)
m Cycling Endurance
– 100,000 cycles per sector typical
m Data Retention
o – 20 years typical
c Device ID
e – JEDEC standard two-byte electronic signature
R – RES command one-byte electronic signature for backward
Not compatibility
CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash devices
Process Technology
– Manufactured on 0.09 µm MirrorBit® process technology
Package Option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 24-ball BGA (6 8 mm) package, 5 5 pin configuration
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power Saving Standby Mode
– Standby Mode 160 µA (typical)
– Deep Power-Down Mode 6 µA (typical)
Memory Protection Features
Memory Protection
– W#/ACC pin works in conjunction with Status Register Bits
to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in
status register configure parts of memory as read-only
Software Features
– SPI Bus Compatible Serial Interface
General Description
This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die. For detailed
specifications, refer to the discrete die datasheet.
Document Name
S25FL129P, 128-Mbit 3.0V Flash Memory Datasheet
Cypress Document Number
002-00648
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00647 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 10, 2016
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