70FL256P0XMFI00 查看數據表（PDF） - Cypress Semiconductor

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70FL256P0XMFI00

256-Mbit 3.0V Flash

Cypress Semiconductor 

S70FL256P

3. Input/Output Description

Signal

I/O

Description

SO/IO1

I/O

Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as

an I/O pin in Dual and Quad I/O, and Quad Page Program modes.

SI/IO0

I/O

Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and

program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual and Quad I/O mode.

SCK

Input

Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising

edge of SCK. Triggers output on SO after the falling edge of SCK.

Chip Selects: Places one of the Flash die in active power mode when driven low. Deselects Flash die

CS1#

CS2#

sign HOLD#/IO3

De W#/ACC/IO2

ew VCC

N GND

Input

I/O

I/O

Input

Input

and places SO at high impedance when high. After power-up, device requires a falling edge on CS1#

and CS2# before any command is written. Device is in standby mode when a program, erase, or Write

Status Register operation is not in progress.

Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is

at high impedance, and all input at SI and SCK are ignored. Requires that CS1# or CS2# also be driven

low. Functions as an I/O pin in Quad I/O mode.

Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low,

prevents any program or erase command from altering the data in the protected memory area.

Functions as an I/O pin in Quad I/O mode.

Supply Voltage

Ground

Not Recommended for 4. Logic Symbol

VCC

SI/IO0

SCK

CS1#

CS2#

W#/ACC/IO2

HOLD#/IO3

SO/IO1

GND

Document Number: 002-00647 Rev. *F

Page 5 of 16

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