M68Z512 查看數據表（PDF） - STMicroelectronics

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M68Z512

4 Mbit (512 Kbit x 8) Low Power SRAM with Output Enable

STMicroelectronics 

Figure 11. Low VCC Data Retention AC Waveforms

5V

VCC

3V

VDR > 2.0V

DATA RETENTION MODE

tCDR

E 2.2V

E ≥ VDR – 0.3V

M68Z512

tER

AI03039

Table 9. Low VCC Data Retention Characteristics

Symbol

Parameter(1)

Test Condition

Min Typ

ICCDR(2) Supply Current (Data Retention)

VCC = 3V, E ≥ VCC – 0.3V

0.4

VDR Supply Voltage (Data Retention)

E ≥ VCC – 0.3V, f = 0

2

tCDR Chip Disable to Power Down

E ≥ VCC – 0.3V, f = 0

0

tER(3) Operation Recovery Time

tAVAV

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

2. Typical condition: TA = 25°C.

3. See Figure 11 for measurement points. Guaranteed but not tested. tAVAV is READ Cycle time.

Max

10

Unit

µA

V

ns

ns

11/15

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