82596CA 查看數據表（PDF） - Intel

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82596CA

HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

Intel 

82596CA

Figure 6 82596 Shared Memory Structure

290218 – 6

82596 SYSTEM MEMORY STRUCTURE

The Shared Memory structure consists of four parts

the Initialization Root the System Control Block the

Command List and the Receive Frame Area (see

Figure 6)

The Initialization Root is in an established location

known to the host CPU and the 82596 (00FFFFF6h)

However the CPU can establish the Initialization

Root in another location by using the CPU Port ac-

cess This root is accessed during initialization and

points to the System Control Block

The System Control Block serves as a bidirectional

mail drop for the host CPU and the 82596 CU and

RU It is the central point through which the CPU and

the 82596 exchange control and status information

The SCB has two areas The first contains instruc-

tions from the CPU to the 82596 These include

control of the CU and RU (Start Abort Suspend

and Resume) a pointer to the list of CU commands

a pointer to the Receive Frame Area a set of Inter-

rupt Acknowledge bits and the T-ON and T-OFF

timers for the bus throttle The second area contains

status information the 82596 is sending to the CPU

Such as the CU and RU states (Idle Active

13

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