AD14160LKB-4 查看數據表（PDF） - Analog Devices
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AD14160LKB-4 Datasheet PDF : 52 Pages
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AD14160/AD14160L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14160/
AD14160L is the bus master accessing external memory space.
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write—Bus
Master below). If these timing requirements are met, the syn-
chronous read/write timing can be ignored (and vice versa).
Parameter
40 MHz–5 V
Min
Max
40 MHz–3.3 V
Min
Max
Units
Timing Requirements:
tDAD
Address, Selects Delay to Data Valid1, 2
17 + DT + W
17 + DT + W
ns
tDRLD
RD Low to Data Valid1
11 + 5DT/8 + W
11 + 5DT/8 + W ns
tHDA
Data Hold from Address3
1.5
1.5
ns
OBSOLETE tHDRH
Data Hold from RD High3
3
tDAAK
ACK Delay from Address2, 4
tDSAK
ACK Delay from RD Low4
3
13 + 7DT/8 + W
7 + DT/2 + W
ns
13 + 7DT/8 + W ns
7 + DT/2 + W ns
Switching Characteristics:
tDRHA
Address Hold After RD High
–1 + H
–1 + H
ns
tDARL
Address to RD Low2
1 + 3DT/8
1 + 3DT/8
ns
tRW
RD Pulsewidth
12.5 + 5DT/8 + W
12.5 + 5DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
7.5 + 3DT/8 + HI
7.5 + 3DT/8 + HI
ns
tSADADC Address Setup Before ADRCLK High2 –0.5 + DT/4
–0.5 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDATI.
2For MSx, SW, BMS, the falling edge is referenced.
3Data Hold: User must meet tHDA or tHDRH or synchronous spec tHDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
4ACK Delay/Setup: User must meet tDSAK or tDAAK or synchronous specification tSACKC.
ADDRESS
MSx, SW
BMS
RD
DATA
ACK
tDARL
tRW
tDAAK
tDAD
tDRLD
tDSAK
tDRHA
tHDA
tHDRH
tRWR
WR, DMAG
ADRCLK
(OUT)
tSADADC
Figure 14. Memory Read—Bus Master
–18–
REV. A
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