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N80C151SA 查看數據表(PDF) - Intel

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N80C151SA Datasheet PDF : 33 Pages
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Symbol
VOH1
VOH2
IIL
ILI
ITL
RRST
CIO
IPD
IDL
ICC
Table 8 DC Characteristics at VCC e 4 5V b 5 5V (Continued)
Parameter
Min
Typical Max Units Test Conditions
Output High Voltage
(Port 0 in External
Address)
Output High Voltage
(Port 2 in External
Address during Page
Mode)
VCC b 0 3
VCC b 0 7
VCC b 1 5
VCC b0 3
VCC b 0 7
VCC b 1 5
V
IOH e b200 mA
IOH e b3 2 mA
IOH e b7 0 mA
V
IOH e b200 mA
IOH e b3 2 mA
IOH e b7 0 mA
Logical 0 Input Cur-
rent (Port 1 2 3)
b50
mA
VIN e 0 45V
Input Leakage Cur-
rent (Port 0)
g10
mA
0 45k VIN k VCC
Logical 1-to-0 Transi-
tion Current (Port 1
2 3)
b650
mA
VIN e 2 0V
RST Pulldown Resistor
40
225
kX
Pin Capacitance
Powerdown Current
10
(Note 4)
pF
FOSC e 16 MHz
TA e 25 C
10
k 20
mA
(Note 4)
Idle Mode Current
13
20
(Note 4)
mA
FOSC e 16 MHz
Operating Current
71
85
(Note 4)
mA
FOSC e 16 MHz
NOTES
1 Under steady-state (non-transient) conditions IOL must be externally limited as follows
Maximum IOL per port pin 10 mA
Maximum IOL per 8-bit port
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions VOL may exceed the related specification Pins are not guaranteed to sink current
greater than the listed test conditions
2 Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0 4V on the low-level outputs of ALE and
ports 1 2 and 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins change from high to low In applications where capacitive loading exceeds 100 pF the noise pulses on these
signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input
logic
3 Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the specification when the
address lines are stabilizing
4 Typical values are obtained using VCC e 5 0 TA e 25 C and are not guaranteed
14

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